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APPLICATION NOTE
SH7211 Group
MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
Introduction
This application note presents sample settings for producing three-phase complementary pulse width modulation (PWM) output, with no overlap of the positive and antiphases, using multi-function timer pulse unit 2 (MTU2) of the SH7211.
Target Device
SH7211
Contents
1. 2. 3. Preface.............................................................................................................................................. 2 Description of the Sample Application .............................................................................................. 4 Documents for Reference ............................................................................................................... 25
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 1. 1.1 Preface Specifications
This application note describes how to use the complementary PWM mode function of multi-function timer pulse unit 2 (MTU2) to output three-phase complementary PWM waveforms. Figure 1 shows the configuration. * Channels 3 and 4 of MTU2 are set to complementary PWM mode (complementary PWM mode 3). * The PWM positive phase output pins are TIOC3B, TIOC4A, and TIOC4B. The antiphase output pins corresponding to these phase output pins are TIOC3D, TIOC4C, and TIOC4D. * The PWM output signal is low-active. * In complementary PWM mode, PWM waveform output incorporates dead time (anti-short periods) to prevent overlap between the positive and antiphases. The dead time is set to 4 m. * The PWM carrier cycle is set to 400 m. * The PWM duty setting values are updated at an interrupt generated every PWM carrier cycle. * A toggle waveform synchronized with the PWM carrier half-cycle is output by pin TIOC3A.
SH7211
SH-2A Interrupt request MTU2 TIOC3A (PB17) TIOC3B (PB18) TIOC3D (PB19) TIOC4A (PB4) TIOC4C (PB6) TIOC4B (PB5) TIOC4D (PB7) Toggle output (synchronized with PWM cycle) PWM output pin 1 (positive phase) PWM output pin 1' (antiphase) PWM output pin 2 (positive phase) PWM output pin 2' (antiphase) PWM output pin 3 (positive phase) PWM output pin 3' (antiphase)
Channels 3 and 4 Complementary PWM mode 3 PWM cycle setting PWM duty setting (x3) Dead time setting
Figure 1 Three-Phase Complementary PWM Output (Complementary PWM Mode 3)
1.2
Module Used
Channels 3 and 4 of multi-function timer pulse unit 2 (MTU2)
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 1.3
MCU: Operating frequencies:
Applicable Conditions
SH7211 [R5F7211] Internal clock (I) = 160 MHz Bus clock (B) = 40 MHz Peripheral clock (P) = 40 MHz MTU2S clock (M) = 80 MHz AD clock (A) = 40 MHz
MCU operating mode: C compiler: Compile options:
Single-chip mode Renesas Technology SuperH RISC engine Family C/C++ Compiler Package, Ver. 9.03, Release 00 High-performance Embedded Workshop default settings (-cpu=sh2a -include="$(WORKSPDIR)\inc" -object="$(CONFIGDIR)\$(FILELEAF).obj" -debug -gbr=auto -chgincpath -errorpath -global_volatile=0 -opt_range=all -infinite_loop=0 -del_vacant_loop=0 -struct_alloc=1 -nologo)
Integrated development environment: Renesas Technology High-performance Embedded Workshop, Ver. 4.05.01.001
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 2. Description of the Sample Application
In this sample application, the complementary PWM mode function of multi-function timer pulse unit 2 (MTU2) is used.
2.1
2.1.1
Operational Overview of Module Used
Multi-Function Timer Pulse Unit 2 (MTU2)
Multi-function timer pulse unit 2 (MTU2) is a multi-function timer unit comprising a 6-channel 16-bit timer. Settings such as compare match or input capture can be made individually for each channel. Channels 3 and 4 can be used for 6line PWM output control by specifying complementary PWM mode or reset synchronous mode. For details of MTU2, see the Multi-Function Timer Pulse Unit 2 (MTU2) section in the SH7211 Group Hardware Manual (RJJ09B0338). Table 1 is an overview of multi-function timer pulse unit 2 (MTU2). Figure 2 is a block diagram of MTU2. Table 1 Overview of Multi-Function Timer Pulse Unit 2 (MTU2) Description 16-bit timer x 6 channels (channels 0 to 5) Each channel selectable among eight counter input clocks (four counter input clocks for channel 5) * Waveform output at compare match, input capture function, counter clear operation, simultaneous write to multiple timer counters (TCNT), simultaneous clear at compare match or input capture * Synchronous register I/O using counter-synchronous operation, max. 12-phase PWM output through combination with synchronous operation * Ability to generate conversion start trigger for A/D converter * Ability to generate interrupt at counter peak/trough and to skip conversion start triggers for A/D converter in complementary PWM mode * Ability to specify register buffer operation for channels 0, 3, and 4 * Ability to specify PWM mode for channels 0 to 4 * Ability to specify phase counting mode independently for channels 1 and 2 * Ability to specify 3-phase positive and negative PWM waveform output (total 6 lines) in complementary PWM mode or reset synchronous PWM mode, using linked operation of channels 3 and 4 * 28 interrupt sources (compare match, input capture, etc.) * Cascade connection operation * High-speed access via internal 16-bit bus * Support for automatic transfer of register data * Ability to specify module standby mode * Support for dead time compensation counter function using channel 5
Item Number of channels Counter clock Operation of channels 0 to 5
Triggers for A/D converter
Buffered operation Operating modes
Interrupt requests Others
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
TIORL TMDR
Channel 3
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D
Control logic for channels 3 and 4
Interrupt request signals Channel 3: TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 Channel 4: TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4
TIORH TIORL
TMDR
Channel 4
TSR
TIER
TCR
TIORH
TOCR
TGCR
TIER
TCR
TCNTS
TCDR
Channel 2
TGRA
TGRB
TCNT
Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 External clock: TCLKA TCLKB TCLKC TCLKD
Module data bus
Input pins Channel 5: TIC5U TIC5V TIC5W
Channel 5
TOER
TDDR TCNTW
TCBR
TGRC
TGRD
TGRA
TGRB
TCNT
Channel 5: TGIU_5 TGIV_5 TGIW_5
TCNTU
TCNTV
TGRW
TGRU
TGRV
TIOR
TIER
TCR
TSR
Control logic
Common
TSYR
Peripheral bus
BUS I/F
TMDR
TSR
TSTR
A/D converter conversion start signal
TIORL
TMDR
Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B
TIORH
Interrupt request signals Channel 0: TGIA_0 TGIB_0 TGIC_0 TGID_0 TGIE_0 TGIF_0 TCIV_0 Channel 1: TGIA_1 TGIB_1 TCIV_1 TCIU_1 Channel 2: TGIA_2 TGIB_2 TCIV_2 TCIU_2
TIOR
Control logic for channels 0 to 2
TMDR
Channel 1
TSR
TIER
TCR
TIOR
Channel 0
TSR
TIER
TCR
TGRA
TGRB TGRC
TCNT
TGRD
TGRA
TGRB
TGRE
[Legend] TSTR: Timer start register TSYR: Timer synchronous register TCR: Timer control register TMDR: Timer mode register TIOR: Timer I/O control register TIORH: Timer I/O control register H TIORL: Timer I/O control register L TIER: Timer interrupt enable register TGCR: Timer gate control register TOER: Timer output master enable register TOCR: Timer output control register TSR: Timer status register TCNT: Timer counter TCNTS: Timer subcounter TCDR: TCBR: TDDR: TGRA: TGRB: TGRC: TGRD: TGRE: TGRF: TGRU: TGRV: TGRW: Timer cycle data register Timer cycle buffer register Timer dead time data register Timer general register A Timer general register B Timer general register C Timer general register D Timer general register E Timer general register F Timer general register U Timer general register V Timer general register W
Figure 2 Block Diagram of MTU2
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TIER
TCR
July 2009
TGRF
TCNT
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
2.1.2 Complementary PWM mode
Multi-function timer pulse unit 2 (MTU2) can be set to complementary PWM mode, in which channels 3 and 4 are used in combination. In complementary PWM mode, three-phase non-overlapping positive and negative PWM waveforms are output. It is also possible to specify PWM waveform output with no dead time to prevent overlapping. Pins TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as PWM output pins in complementary PWM mode. The TIOC3A pin can be set for toggle output synchronized with the PWM cycle. Figure 3 shows the configuration of channels 3 and 4 of multi-function timer pulse unit 2 (MTU2) in complementary PWM mode.
TCNT_4 underflow interrupt
TGRA_3 comparematch interrupt
TGRC_3
TCBR
TDDR
TGRA_3
TCDR
Comparator
Output controller
Match signal
PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2 POE3
Comparator
Match signal
TGRB_3
TGRA_4
TGRD_3
TGRC_4
TGRD_4
TGRB_4
Temp 2
Temp 3
Temp 1
External cutoff interrupt
: Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by TRWER) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read)
Figure 3 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
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Output protection circuit
TCNT_3
TCNTS
TCNT_4
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
The channel 3 and channel 4 register functions in complementary PWM mode are described below. * Timer general register A_3 (TGRA_3) operates as a compare register. The upper limit value for TCNT_3 (1/2 carrier cycle + dead time) is set in TGRA_3. To change the value of this register while the timer is operating, set the new value in timer general register C_3 (TGRC_3). * Timer general register B_3 (TGRB_3) operates as a compare register. The duty of the PWM waveforms output by pins TIOC3B and TIOC3D is set in TGRB_3. To change the value of this register while the timer is operating, set the new value in timer general register D_3 (TGRD_3). * Timer general register C_3 (TGRC_3) operates as the buffer register for TGRA_3. While the timer is operating, TGRA_3 is updated to reflect values set in TGRC_3. * Timer general register D_3 (TGRD_3) operates as the buffer register for TGRB_3. While the timer is operating, TGRB_3 is updated to reflect values set in TGRD_3. * Timer general register A_4 (TGRA_4) operates as a compare register. The duty of the PWM waveforms output by pins TIOC4A and TIOC4C is set in TGRA_4. To change the value of this register while the timer is operating, set the new value in timer general register C_4 (TGRC_4). * Timer general register B_4 (TGRB_4) operates as a compare register. The duty of the PWM waveforms output by pins TIOC4B and TIOC4D is set in TGRB_4. To change the value of this register while the timer is operating, set the new value in timer general register D_4 (TGRD_4). * Timer general register C_4 (TGRC_4) operates as the buffer register for TGRA_4. While the timer is operating, TGRA_4 is updated to reflect values set in TGRC_4. * Timer general register D_4 (TGRD_4) operates as the buffer register for TGRB_4. While the timer is operating, TGRB_4 is updated to reflect values set in TGRD_4. * Temporary registers 1, 2, and 3 (Temp1, 2, and 3) occupy a position between the buffer registers and compare registers. Data written to the buffer register is transferred to the temporary register and then to the compare register. The temporary registers cannot be accessed by the CPU. * Timer counter_3 (TCNT_3) is a 16-bit counter. TCNT_3 starts counting down when a compare match with TGRA_3 occurs, and it starts counting up when a compare match with the timer dead time data register (TDDR) occurs. * Timer counter_4 (TCNT_4) is a 16-bit counter. TCNT_4 starts counting down when a compare match with the timer cycle data register (TCDR) occurs, and it starts counting up when the value of TCNT_4 reaches H'0000. * The timer dead time data register (TDDR) is a 16-bit readable/writable register. TDDR specifies the dead time for the PWM waveforms. * The timer cycle data register (TCDR) is a 16-bit register. TCDR specifies a value equal to one-half the PWM carrier cycle. * The timer cycle buffer register (TCBR) operates as the buffer register for TCDR. While the timer is operating, TCDR is updated to reflect values set in TCBR.
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 2.2
2.2.1
Operation of the Sample Program
Settings for Operation of the Sample Program
In this application note, channels 3 and 4 of the multi-function timer pulse unit 2 (MTU2) are set to complementary PWM mode 3 and three-phase complementary PWM waveforms are output. In addition, toggle output synchronized with the PWM carrier cycle is generated. Table 2 lists the setting conditions for complementary PWM mode operation. Figure 4 shows a sample of output waveforms in complementary PWM mode. Table 2 Setting for Operation in Complementary PWM Mode Description Channels 3 and 4 Complementary PWM mode 4 (data transfer at counter peaks and troughs) * TIOC3A pin: Toggle output synchronized to PWM cycle * TIOC3B pin: PWM output 1 (positive phase waveform) * TIOC3D pin: PWM output 1' (PWM output 1 antiphase waveform) * TIOC4A pin: PWM output 2 (positive phase waveform) * TIOC4C pin: PWM output 2' (PWM output 2 antiphase waveform) * TIOC4B pin: PWM output 3 (positive phase waveform) * TIOC4D pin: PWM output 4' (PWM output 3 antiphase waveform) * Positive phase output: Low-active output * Antiphase output: Low-active output 10 MHz (4 cycles of P clock) 400 m (carrier frequency: 2.5 kHz) 4 m * For PWM outputs 1, 2, and 3, the initial PWM duty is 50%. * The PWM duty is updated by an interrupt generated at every compare match with TGRA_3. (The setting value is incremented or decremented.) * TGRA_3 compare match interrupt A compare match with TGRA_3 occurs every PWM carrier cycle.
Item Channels in use Operating mode Functions of pins
Active level Counter clock PWM carrier cycle Dead time PWM duty
Interrupt
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
Figure 4 Output Waveforms in Complementary PWM Mode Operation
2.2.2
Description of Operation by the Sample Program
(1) Operation of Timer Counters Figure 5 shows the operation timer counter in complementary PWM mode. Counters TCNT_3 and TCNT_4, which correspond to channel 3 and channel 4, each count up or down. The initial value of counter TCNT_3 is set to the same value as the TDDR register, and the initial value of counter TCNT_4 is set to H'0000. Channels 3 and 4 start timer count operation simultaneously.
Figure 5 Operation of Timer Counters
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
(2) PWM Output Waveforms The three-phase complementary PWM output waveforms are controlled by using the compare match function with timer counters (TCNT_3 and TCNT_4) and compare registers (TGRB_3, TGRA_4, and TGRB_4). When the value of a register matches the value of a counter, positive phase output and antiphase output are generated according to the values set in bits OLSN and OLSP in the timer output control register (TOCR). Figure 6 shows the output waveforms for single-phase (positive phase, antiphase) complementary PWM output. The positive phase and antiphase output signals are controlled by using the compare match function with timer counters (TCNT_3 and TCNT_4) and a compare register (TGRB_3).
: TGRB_3 (compare register) PWM output 1 and PWM output 1' timing update : TGRB_3 compare match TCNTS: Sub-counter TCNTS TCNT_3 TCNT_4 TGRB_3
TCNT_3, TCNT_4 TGRA_3 TCDR
TDDR H'0000
Dead time TIOC3B pin 1 (PWM output 1 positive phase) 0 TIOC3D pin 1 (PWM output 1' antiphase) 0 Output antiphase 1 at compare match of up-counting TCNT_3 and TGRB_3. Output positive phase 0 at compare match of up-counting TCNT_4 and TGRB_3.
Dead time
Output antiphase 0 at compare match of down-counting TCNT_3 and TGRB_3. Output positive phase 1 at compare match of down-counting TCNT_4 and TGRB_3.
The PWM output waveforms are low-active (positive phase and antiphase). : Active level (low level)
Figure 6 Complementary PWM Output Waveforms
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
(3) Changing the PWM Duty Figure 7 shows the PWM duty update timing. In the reference program, the TGRA_3 compare match interrupt (counter peak interrupt) handler makes register settings after incrementing or decrementing the PWM duty setting values. Three buffer registers, TGRD_3, TGRC_4, and TGRD_4, are used to update the PWM duty. When changing the duty, always set TGRD_4 last. Always execute a write to TGRD_4 after writing updated register data, even if the TGRD_4 data value does not change.
: TGRD_3 (buffer register) : Temp (TGRB_3 temporary register) : TGRB_3 (compare register) : TGRB_3 compare match TCNTS: Sub-counter TCNTS TCNT_3 TGRD_3 TGRB_3 TCNT_4
TCNT_3, TCNT_4 TGRA_3 TCDR
TDDR H'0000 Note: The operation mode is complementary PWM mode 3 (transfer at peak and trough)
TGRA_3 interrupt flag TGRA_3 interrupt handler (data update) TGRD_3 buffer register Temporary register TGRB_3 compare register Update register value (data2) data1 data1 data1 data2 data2 (data1) (data2) data2 Update register value (data3) data3 data3 (data2)
(data3) data3
Figure 7 PWM Duty Update Timing (4) Output Toggling in Synchronization with PWM Cycle Figure 8 shows the operations for toggling of an output level in synchronization with the PWM cycle. The PSYE bit in the timer output control register (TOCR) is set to 1 to select toggling of an output in synchronization with the PWM carrier cycle. Toggling is of the signal on the TIOC3A pin. The initial value for output is 1.
TCNT_3, TCNT_4 Output level is toggled on compare match with H'0000. TGRA_3 TCDR TCNT_3
TCNT_4 TDDR H'0000 Carrier cycle TIOC3A pin (toggle output) 1 0 Output level is toggled on compare match with H'0000.
Figure 8 Operation for Toggling an Output in Synchronization with the PWM Cycle REJ06B0891-0100/Rev.1.00 July 2009 Page 11 of 26
SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
2.2.3 Example of Output with User-Defined PWM Duty
Table 3 summarizes single-phase positive phase and antiphase output operation, showing the relationship between different PWM duty setting values and the resulting positive phase and antiphase output waveforms. In complementary PWM mode, the output levels are fixed when the value of the compare register (TGRB_3) is H'0000, with positive phase output in a constant-on state and antiphase output in a constant-off state. The output levels are also fixed when the value of the compare register (TGRB_3) is equal to or greater than the setting value of the TGRA_3 register, with positive phase output in a constant-off state and antiphase output in a constant-on state. Figures 9 and 10 show examples of positive phase and antiphase output waveforms. Note that when the PWM duty is changed, the new setting value is not written directly to the compare register. Instead, it must be written to the buffer register, after which the compare register is updated via the buffer register. Table 3 Example of PWM Duty Settings and Output Waveforms Output Waveform* Positive Phase Output (TIOC3B Pin) Constant-off state (high) Constant-off state (high) Constant-off state (high) On waveform output (pulse) Antiphase Output (TIOC3D Pin) Constant-on state (low) Off waveform output (pulse) Off waveform output (width of dead time x 2) Off waveform output Waveform Figure Figure 9 (a) -- Figure 9 (b) -- Figure 9 (c) -- Figure 10 (a) --
TGRB_3 Register Value TGRB_3 TGRA_3 Between TGRA_3 and TCDR TGRB_3 = TCDR Between (TCDR - Td) and TCDR TGRB_3 = (TCDR - Td) Between (TDDR x 2) and (TCDR - Td) TGRB_3 = (TDDR x 2) Between TDDR and (TDDR x 2) TGRB_3 = TDDR
On waveform output (width Off waveform output (width of dead time x 2) of dead time x 4) Complementary PWM waveform output Off waveform output (width of dead time x 4) Off waveform output On waveform output (width of dead time x 2) On waveform output (pulse)
Figure 10 (b) On waveform output (width Constant-off state (high) of dead time x 2) Between H'0000 and TDDR Off waveform output (pulse) Constant-off state (high) -- TGRB_3 = H'0000 Constant-on state (low) Constant-off state (high) Figure 10 (c) Note: * The PWM output active level is set to low. The example is for single-phase (positive phase, antiphase) complementary PWM output.
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
TGRB_3: Compare register value (a) TGRB_3 = TGRA_3 TCNT_3, TCNT_4 : Active level (low level) Td: Dead time setting TCNTS: Sub-counter TCNTS
TGRB_3 (=TGRA_3) TGRA_3 TCDR Td
TCNT_3 TCNT_4 TDDR H'0000
TIOC3B pin (PWM 1 output 1 positive phase) 0 TIOC3D pin (PWM output 1 1' antiphase) 0
Constant-off (high) Constant-on (low)
(b) TGRB_3 = TCDR
TCNT_3, TCNT_4 TGRA_3
TGRB_3 (=TCDR) TCDR
Td
TCNTS
TCNT_3 TCNT_4 TDDR H'0000 Dead time TIOC3B pin (PWM 1 output 1 positive phase) 0 TIOC3D pin (PWM output 1 1' antiphase) 0 (c) TGRB_3 = TCDR-Td Constant-off (high) ON (Low) OFF OFF Dead time Dead time Dead time
TCNT_3, TCNT_4 TGRA_3 TCDR Td Td TCNTS
TGRB_3 (=TCDR-Td)
TCNT_3 TCNT_4 TDDR H'0000 Dead time TIOC3B pin (PWM 1 output 1 positive phase) 0 TIOC3D pin (PWM output 1 1' antiphase) 0 OFF (High) ON (Low) ON OFF Dead time OFF
OFF
Figure 9 Examples of PWM Waveform Output (1)
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
TGRB_3: Compare register value (a) TGRB_3 = 2 * TDDR TCNT_3, TCNT_4 TGRA_3 TCDR TCNTS : Active level (low level) Td: Dead time setting TCNTS: Sub-counter
TCNT_3 TCNT_4 TGRB_3 (=2*TDDR) TDDR H'0000 Td Td
TIOC3B pin (PWM 1 output 1 positive phase) 0 TIOC3D pin (PWM output 1 1' antiphase) 0
OFF ON
ON OFF
OFF ON
OFF ON
(b) TGRB_3 = TDDR
TCNT_3, TCNT_4 TGRA_3 TCDR TCNTS
TCNT_3 TCNT_4 TGRB_3 (=TDDR) TDDR H'0000 Td
TIOC3B pin (PWM 1 output 1 positive phase) 0 TIOC3D pin (PWM output 1 1' antiphase) 0 (c) TGRB_3 = H'0000 TCNT_3, TCNT_4 TGRA_3 TCDR
ON Constant-off (always high)
OFF
ON
OFF
TGRB_3: Compare register value TCNTS
TCNT_3 TCNT_4 TDDR TGRB_3 (=H'0000) H'0000 Td
TIOC3B pin (PWM output 1 positive phase) TIOC3D pin (PWM output 1' antiphase)
1 0 1 0
Constant-on (always low) Constant-off (always high)
Figure 10 Examples of PWM Waveform Output (2)
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 2.3
2.3.1
Configuration of the Sample Program
Description of Functions
Table 4 lists functions used in this sample program. Table 4 Functions Used Label main () Description Makes initial settings for each module and makes timer start settings for multi-function timer pulse unit 2 (MTU2). Cancels MTU2 module standby. Makes MTU2 (channels 3 and 4) initial settings. Specifies reset-synchronized PWM mode. Makes initial settings for the pin function controller (PFC). Sets MTU2-related pins to timer pin function. Handler for the MTU2 (channel 3) TGRA_3 compare match interrupt. Updates the three-phase PWM duty setting values. The interrupt is generated once every PWM carrier cycle (400 m).
Function Name Main
Standby setting function MTU2 initial setting function PFC initial setting function TGRA_3 interrupt function
stbcr_init () mtu2_init () pfc_init () int_mtu2_tgia3 ()
2.3.2
Variable Usage
Table 5 lists the functions used by the sample program. Table 5 Variable Usage Description Dead time setting value (TDDR register setting value) Value equal to 1/2 of PWM carrier cycle (TCBR register setting value) Value equal to 1/2 of PWM carrier cycle + dead time (TGRC_3 register setting value) PWM1 output (TIOC3B pin and TIOC3D pin) PWM duty setting value (TGRD_3 register setting value) PWM2 output (TIOC4A pin and TIOC4C pin) PWM duty setting value (TGRC_4 register setting value) PWM3 output (TIOC4B pin and TIOC4D pin) PWM duty setting value (TGRD_4 register setting value) Name of Employing Module * mtu2_init ()
Label Name Dead_time C_cycle Pul_cycle Pul_pwm_duty1 Pul_pwm_duty2 Pul_pwm_duty3
* mtu2_init () * int_mtu2_tgia3 ()
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 2.4 Procedure for Setting the Module Used
The processing sequences of the sample program are shown below.
2.4.1
Main Function
Figure 11 shows the processing sequence of the main function.
main()
0Duty_select
[1]
[1] Initialize variable. Initialize PWM duty update flag (Duty_select). [2] Clear on-chip peripheral function module standby mode. [3] Initial settings for multi-function timer pulse unit 2 (MTU2)
Execute initial standby setting function stbcr_init() Execute MTU2 initial settings function mtu2_init()
[2]
[3]
[4] Make interrupt controller (INTC) settings. Set the interrupt priority level for MTU2 interrupt sources (TGI3A to TGI3D) to D'15 (H'F). [5] Make pin function controller (PFC) initial settings. [6] Make MTU2 timer start register (TSTR) settings. CST4 bit = B'1: Set timer counter TCNT_4 to count operation. CST3 bit = B'1: Set timer counter TCNT_3 to count operation. Set bits CST3 and CST4 at the same time. [7] Clear interrupt mask bit to 0. Enable CPU interrupts at all interrupt priority levels.
Set interrupt priority level setting register 10 (IPR10) Execute PFC initial settings function pfc_init()
[4]
[5]
Set timer start register (TSTR)
[6]
Clear interrupt mask set_imask(0)
[7]
Figure 11 Processing by Function main
2.4.2
Initialization for Standby
Figure 12 shows the flow of processing for standby processing.
stbcr_init()
Set standby control register 3 (STBCR3) END
[1]
[1] Cancel module standby mode. MSTP35 bit = B'0: Enable clock supply to MTU2.
Figure 12 Initialization: Release from Standby
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
2.4.3 Initialization of Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 13 shows the processing sequence of the function that makes initial settings for multi-function timer pulse unit 2 (MTU2). Channels 3 and 4 of are set to complementary PWM mode 3.
Figure 13 Initialization of MTU2
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
2.4.4 Initialization of Pin Function Controller (PFC)
Figure 14 shows the flow for initialization of the PFC.
Figure 14 Initialization of Pin Function Controller (PFC)
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
2.4.5 Handling of the Compare Match Interrupt
Figure 15 shows the flow for handling the compare match interrupt (TGRA_3) from MTU2.
int_mtu2_tgia3() Clear TGRA3 interrupt flag [2] Pul_pwm_duty1 == 0 ? Yes [1] No [3] No Pul_pwm_duty1 cycle? Yes 0 Duty_select (set increment) [4] Duty_select == 0 Yes [Increment duty setting value] Pul_pwm_duty1 ++ Pul_pwm_duty2 ++ Pul_pwm_duty3 ++ [Decrement duty setting value] Pul_pwm_duty1 -Pul_pwm_duty2 -Pul_pwm_duty3 -? 1 Duty_select (set decrement) [2][3] Set flag. Set PWM duty increment/decrement flag (Duty_select variable). Set to increment (0 Duty_select) when duty is 0. Set to decrement (1 Duty_select) when duty is 1. [4] Check flag Switch to incrementing or decrementing of PWM duty setting value. [1] Clear interrupt source flag. TGFA bit = B'0: Clear timer status register_3 (TSR_3) compare flag A. To clear the flag, write 0 after reading the bit as 1.
No
Pul_pwm_duty1 TGRD_3 Pul_pwm_duty2 TGRC_4 Pul_pwm_duty3 TGRD_4 END
[5]
[5] Set PWM duty in register. Buffer register TGRD_3: Set PWM1 output (positive phase, antiphase) duty. Buffer register TGRC_4: Set PWM2 output (positive phase, antiphase) duty. Buffer register TGRD_4: Set PWM3 output (positive phase, antiphase) duty.
Figure 15 Interrupt Handling
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 2.5 Settings of Registers in the Sample Program
The following describes the settings of registers used in the sample program.
2.5.1
Clock Pulse Generator (CPG)
Table 6 gives a list of settings for registers of the clock pulse generator (CPG). Table 6 Clock Pulse Generator (CPG) Address H'FFFE0010 Setting H'1303 Description Specifies the clock output settings and operating frequency multiplication ratios. * CKOEN = B'1: Fix CK pin low level. * STC1 and STC0 = B'11: PLL circuit 1 x 2 * IFC2 to IFC0 = B'000: Internal clock (I) x 1 * RNGS = B'0: High-frequency mode * PFC2 to PFC0 = B'011: Peripheral clock (P) x 1/4
Register Name Frequency control register (FRQCR)
2.5.2
Power-Down Mode
Table 7 shows the register settings for power down mode. Table 7 Power-Down Mode Address H'FFFE0408 Setting H'5E Description Specifies the operation settings for individual modules. * HIZ= B'0: Maintain pin state in software standby mode. * MSTP36 = B'1: Stop clock supply to MTU2S. * MSTP35 = B'0: Operate MTU2. * MSTP34 = B'1: Stop clock supply to POE2. * MSTP33 = B'1: Stop clock supply to IIC3. * MSTP32 = B'1: Stop clock supply to ADC. * MSTP31 = B'1: Stop clock supply to DAC. * MSTP30 = B'0: Operate flash memory.
Register Name Standby control register 3 (STBCR3)
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2.5.3 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 8 gives a list of settings for registers of multi-function timer pulse unit 2 (MTU2). Table 8 Multi-Function Timer Pulse Unit 2 (MTU2) Address H'FFFE4200 Value H'01 Description TCNT control settings * CCLR2 to CCLR0 = B'000: Disable clearing of TCNT. * CKEG1 and CKEG0 = B'00: Count at rising edge. * TPSC2 to TPSC0 = B'001: TCNT counts using internal clock P / 4. TCNT control settings * CCLR2 to CCLR0 = B'000: Disable clearing of TCNT. * CKEG1 and CKEG0 = B'00: Count at rising edge. * TPSC2 to TPSC0 = B'001: TCNT counts using internal clock P / 4. 16 bit counter In complementary PWM mode, set the initial value to match the setting value of the timer dead time data register (TDDR). 16 bit counter Set the initial value to H'0000. In complementary PWM mode, set the TCNT_3 upper limit to a value of (1/2 carrier cycle + dead time). In complementary PWM mode, set the initial value of the TGRA_3 buffer register to match the setting value of the TGRA_3 register. In complementary PWM mode, set the PWM output 1 compare register PWM duty (initial output value). In complementary PWM mode, set the initial value of the TGRB_3 buffer register to match the setting value of the TGRB_3 register. New PWM duty values are set in this register. In complementary PWM mode, set the PWM output 2 compare register PWM duty (initial output value). In complementary PWM mode, set the initial value of the TGRA_4 buffer register to match the setting value of the TGRA_4 register. New PWM duty values are set in this register. In complementary PWM mode, set the PWM output 3 compare register PWM duty (initial output value).
Register Name Timer control register_3 (TCR_3)
Timer control register_4 (TCR_4)
H'FFFE4201
H'01
Timer counter_3 (TCNT_3)
H'FFFE4210
D'40
Timer counter_4 (TCNT_4) Timer general register A_3 (TGRA_3) Timer general register C_3 (TGRC_3) Timer general register B_3 (TGRB_3) Timer general register D_3 (TGRD_3)
H'FFFE4212 H'FFFE4218
H'0000 D'2040
H'FFFE4224
H'FFFE421A
D'1020
H'FFFE4226
Timer general register A_4 (TGRA_4) Timer general register C_4 (TGRC_4)
H'FFFE421C
D'1020
H'FFFE4228
Timer general register B_4 (TGRB_4)
H'FFFE421E
D'1020
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
Register Name Timer general register D_4 (TGRD_4) Address H'FFFE422A Value D'1020 Description In complementary PWM mode, set the initial value of the TGRB_4 buffer register to match the setting value of the TGRB_4 register. New PWM duty values are set in this register. This 16-bit register is only used in complementary PWM mode. Set the offset value (dead time value) for TCNT_4 and TCNT_3. This register is only used in complementary PWM mode. Set the TCNT_4 upper limit value (1/2 the carrier cycle). This register is only used in complementary PWM mode. It functions as the buffer register for the TCDR register. Set the same value as that for the TCDR register. Complementary PWM mode output operation settings * PSYE = B'1: Enable toggle output synchronized with the PWM cycle. * TOCL = B'0: Enable writing to the TOCS, OLSN, and OLSP bits. * TOCS = B'0: Enable TOCR1 setting. * OLSN = B'0: In complementary PWM mode, select the antiphase output level: Initial output = high, active level = low. * OLSP = B'0: In complementary PWM mode, select the positive phase output level: Initial output = high, active level = low. Sets the operation mode (channel 3). * BFB = B'1: Set TGRB and TGRD to buffer operation. * BFA = B'1: Set TGRA and TGRC to buffer operation. * MD3 to MD0 = B'1111: Complementary PWM mode 3 (transfer at peak and trough) Sets the operation mode (channel 4). When channel 3 is set to complementary PWM mode, the settings for channel 4 are ignored and the settings for channel 3 are followed automatically. There is no need to make setting to this register. Leave the initial values unchanged.
Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR)
H'FFFE4216
D'40
H'FFFE4214
D'2000
H'FFFE4222
Timer output control register 1 (TOCR1)
H'FFFE420E
H'40
Timer mode register_3 (TMDR_3)
H'FFFE4202
H'3F
Timer mode register_4 (TMDR_4)
H'FFFE4203
-
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
Register Name Timer output master enable register (TOER) Address H'FFFE420A Value H'FF Description Specifies the output settings for the MTU2 output pins. * OE4D = B'1: Enable MTU2 output on TIOC4D pin. * OE4C = B'1: Enable MTU2 output on TIOC4C pin. * OE3D = B'1: Enable MTU2 output on TIOC3D pin. * OE4B = B'1: Enable MTU2 output on TIOC4B pin. * OE4A = B'1: Enable MTU2 output on TIOC4A pin. * OE3B = B'1: Enable MTU2 output on TIOC3B pin. Enables or disables interrupt requests. * TGIEA= B'1: Enable interrupt requests (TGIA) by TGFA bit. Starts or stops TCNT operation for channels 0 to 4. * CST4 = B'1: Start TCNT_4 count operation. * CST3 = B'1: Start TCNT_3 count operation. Stop count operation by TCNT_2, TCNT_1, and TCNT_0. Make counter operation bit settings for TCNT_4 and TCNT_3 at the same time.
Timer interrupt enable register_3 (TIER_3) Timer start register (TSTR)
H'FFFE4208
H'01
H'FFFE4280
H'C0
2.5.4
Interrupt Controller (INTC)
Table 9 gives a list of settings for registers of the interrupt controller (INTC). Table 9 Interrupt Controller (INTC) Address H'FFFE0C08 Setting H'00F0 Description Sets interrupt priority levels (level 0 to 15). * Bits 15 to 12 = B'0000: MTU2 (TGI2A and TGI2B) interrupt level = 0 * Bits 11 to 8 = B'0000: MTU2 (TCI2V and TCI2U) interrupt level = 0 * Bits 7 to 4 = B'1111: MTU3 (TGI3A to TGI3D) interrupt level = 15 * Bits 3 to 0 = B'0000: MTU3 (TCI3V) interrupt level = 0 The TGI3A interrupt is used by the reference program.
Register Name Interrupt priority level setting register 10 (IPR10)
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
2.5.5 Pin Function Controller (PFC)
Table 10 gives a list of settings for registers of the pin function controller (PFC). Table 10 Pin Function Controller (PFC) Register Name Port B control register L2 (PBCRL2) Address H'FFFE3894 Setting H'4444 Description Sets port B multiplexed pin functions. * PB7MD2 to PB7MD0 = B'100: Set PB7 to TIOC4D I/O (MTU2). * PB6MD2 to PB6MD0 = B'100: Set PB6 to TIOC4C I/O (MTU2). * PB5MD2 to PB5MD0 = B'100: Set PB5 to TIOC4B I/O (MTU2). * PB4MD2 to PB4MD0 = B'100: Set PB4 to TIOC4A I/O (MTU2). Sets port B multiplexed pin functions. * PB19MD2 to PB19MD0 = B'100: Set PB19 to TIOC3D I/O (MTU2). * PB18MD2 to PB18MD0 = B'100: Set PB18 to TIOC3C I/O (MTU2). * PB17MD2 to PB17MD0 = B'100: Set PB17 to TIOC3B I/O (MTU2). * PB16MD2 to PB16MD0 = B'000: Set PB16 to TIOC3A I/O (MTU2). Sets port B pin I/O directions. * PB19IOR = B'1: Set PB19 (TIOC3D) as an output pin. * PB18IOR = B'1: Set PB18 (TIOC3B) as an output pin. * PB17IOR = B'1: Set PB17 (TIOC3A) as an output pin. * PB16IOR = B'0: Set PB16 (port) as an input pin. Set all the others to B'0: All input pins. Sets port B pin I/O directions. * PB7IOR = B'1: Set PB7 (TIOC4D) as an output pin. * PB6IOR = B'1: Set PB6 (TIOC4C) as an output pin. * PB5IOR = B'1: Set PB5 (TIOC4B) as an output pin. * PB4IOR = B'1: Set PB4 (TIOC4A) as an output pin. Set all the others to B'0: All input pins.
Port B control register H1 (PBCRH1)
H'FFFE388E
H'4440
Port B I/O register H (PBIORH)
H'FFFE3884
H'000E
Port B I/O register L (PBIORL)
H'FFFE3886
H'00F0
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode) 3. Documents for Reference
* Hardware Manual SH7211 Group Hardware Manual [RJJ09B0338] (The latest version can be downloaded from the Renesas Technology Web site.) * Software Manual SH-2A/SH2A-FPU Software Manual [RJJ09B0086] (The latest version can be downloaded from the Renesas Technology Web site.)
Website and Support
Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com
Revision Record
Rev. 1.00 Date Jul.16.09 Description Page Summary -- First edition issued
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SH7211 Group MTU2 Three-Phase Complementary PWM Output Function (Complementary PWM Mode)
Notes regarding these materials
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